Cmos Process to Reduce Costs and Improve Energy Efficiency, and Then Explores the Logical and Physical Implications of Leveraging This

......Modern embedded, server, graphics, and network processors already include tens to hundreds of cores on a single die, and this number will continue to increase over the next decade. Corresponding increases in main memory bandwidth are also required, however, if the greater core count is to result in improved application performance. Projected enhancements of existing electrical DRAM interfaces are not expected to supply sufficient bandwidth with reasonable power consumption and packaging cost. To meet this many-core memory bandwidth challenge, we are combining monolithic CMOS silicon photonics with an optimized processor-memory network architecture. Existing approaches to on-chip photonic interconnect have required extensive process customizations, some of which are problematic for integration with many-core processors and memories. In contrast, we are developing new photonic devices that use the existing material layers and structures in a standard bulk CMOS flow. In addition to preserving the massive investment in standard fabrication technology, monolithic integration reduces the area and energy costs of interfacing electrical and optical components. Our technology supports dense wavelength-division multiplexing (DWDM) with dozens of wavelengths packed onto the same waveguide to further improve area and energy efficiency. The challenge when designing a photonic chip-level network is to turn the raw linklevel benefits of energy-efficient DWDM photonics into system-level performance improvements. Previous approaches have used photonics for intrachip circuit-switched networks with very large messages, intrachip Christopher Batten Ajay Joshi Jason Orcutt Anatol Khilo Benjamin Moss Charles W. Holzwarth Miloš A. Popović Hanqing Li Henry I. Smith Judy L. Hoyt Franz X. Kärtner Rajeev J. Ram Vladimir Stojanović Massachusetts Institute of Technology